IMPLEMENTATION OF MULTIPLIER ON SPARTAN-2 FPGA AS DIGITAL FILTER SUPPORT ON RADIO DETECTION FINDER (RDF)

Abstract

ABSTRACT

Multipliers are one of the most important parts of a device that can affect the performance of digital devices. High speed and efficient multiplier systems are important factors for designers of microprocessor devices, microcontrollers and the like. Field Programmable Gate Arrays (FPGAs) have emerged as the preferred platform for efficient and flexible hardware implementation.

This research provides an analysis of the multiplier algorithm for LPF (Low Pass Filter) digital filter implementation output using the hamming window method with FPGA chip design on Xillinx 10.1 software. This method is used to design multiplier FPGA chips to support the LPF digital filter applied to radio direction finders (RDF) so that it is expected that this digital filter performance will be even better.

Based on this research, the results of the observation show that filter responses are in accordance with the design specifications but there are errors between the results of the theory and the simulation and implementation of the tool. The biggest error is 52.32% at the 4th coefficient (0.01748) and the smallest error is 0.72% at the 1st coefficient (0.31478).

Keywords: Spartan2 FPGA, Xilinx ISE 10.1, Digital Filter, Multiplier, Hamming Window.